The Water Behind India's Chip Ambitions

India's semiconductor programme has moved from announcement to physical construction at a pace that would have seemed unlikely two years ago. In Dholera, Gujarat, Tata Electronics and Taiwan's Powerchip Semiconductor Manufacturing Corporation have a joint fabrication plant with construction 50 percent complete as of April 2026, targeting first silicon by late 2026 and full commercial operations by 2028. The planned capacity is 50,000 wafer starts per month at the 28nm process node. In Sanand, Micron Technology inaugurated its Assembly, Test and Packaging facility on February 28, 2026, the first operational semiconductor facility of the current mission cycle. In Morigaon, Assam, a Tata Electronics OSAT plant designed for high-volume chip packaging is moving toward pilot production. Rajasthan commissioned its first semiconductor assembly plant in Bhiwadi in May 2026..These are buildings with underground foundations, equipment on order, and international partnerships signed. Budget 2026-27 allocated Rs 8,000 crore to the semiconductor mission, the largest single-year outlay since the programme launched. The India Semiconductor Mission (ISM) website recorded the commencement of commercial production at both Micron and Kaynes Semicon OSAT facilities in Sanand. The NITI Aayog released India's semiconductor industry roadmap on May 29, 2026, laying out a 10-year trajectory toward technological depth and sovereign intellectual property in chip manufacturing..Behind each of these milestones sits an infrastructure requirement that rarely appears in semiconductor headlines: water. Specifically, ultra-pure water, or UPW. At Dholera's planned peak capacity of 50,000 wafers per month, the fab will require approximately 1,500 gallons of UPW and around 2,200 gallons of water in total for every 300mm wafer processed. Daily water demand at full utilisation will run at 3 to 4 million gallons of municipal input, of which approximately 2 to 2.5 million gallons will be produced as UPW for direct process contact. This demand is recurring and year-round; it does not scale down during slower production phases because the UPW loop must run continuously to prevent quality degradation..That demand will be placed on Gujarat's Narmada canal system and Dholera's treatment infrastructure, in a country where per capita water availability has declined steadily from 1,816 cubic metres in 2001 to 1,486 cubic metres in 2021, and is projected by the Central Water Commission to fall further to 1,367 cubic metres by 2031. India is already in water-stressed territory by international classification — the threshold is 1,700 cubic metres per person per year..The chart above uses Central Water Commission data published in 2019 and cited in the International Journal of Science and Technology (2025). India's per capita availability is declining because population growth is outpacing the fixed stock of utilisable water resources. The country's total utilisable water resources are estimated at 1,123 billion cubic metres, a figure that does not change with population. As of 2025, projected availability sits at approximately 1,401 cubic metres per person per year, within the water-stressed range..Gujarat's position within this national picture is particularly relevant for semiconductor infrastructure planning. The Central Ground Water Board's assessments consistently show that a large proportion of Gujarat's districts are affected by salinity, fluoride, or nitrate contamination in groundwater, particularly in coastal, arid, and semi-arid zones. Dholera sits in a coastal zone where local rivers are seasonal. The Dholera Special Investment Region's water master plan identifies the Narmada Canal as the primary source, supplemented by water treatment infrastructure at Ottariya and Hebatpur. Gujarat's semiconductor policy has set an industrial water tariff of Rs 12 per cubic metre for the first five years a reasonable incentive, but one that does not resolve the volume and quality questions that UPW system design requires to be answered.What ultra-pure water is, and why it determines chip yieldThe term ultra-pure water understates the precision involved. UPW used in semiconductor manufacturing must reach a resistivity of 18.2 megaohm-centimetres at 25 degrees Celsius, the theoretical maximum purity of water at that temperature. Total organic carbon must be below one part per billion. Particle counts must stay under one particle per millilitre for particles larger than 0.05 microns. Bacteria must be non-detectable at 0.1 colony-forming units per millilitre. Dissolved oxygen and dissolved silica are controlled at parts-per-trillion levels for advanced nodes..Municipal drinking water in Indian cities typically has a resistivity between 0.001 and 0.003 megaohm-centimetres. The gap between that and semiconductor-grade UPW is six orders of magnitude. Even pharmaceutical-grade water for injectables falls well short of semiconductor UPW specifications. The reason for this standard is geometry: the transistors being fabricated at the 28nm node targeted at Dholera are smaller than most viruses. A metal ion, a trace dissolved mineral, or a particle deposited on a wafer surface at the wrong process step can destroy the circuit pattern being etched..Yield: the proportion of functional chips per wafer is the central economic variable in chip manufacturing. Water quality is a direct determinant of yield. It is not a utility consideration..UPW is used at every stage of wafer fabrication. During oxidation, it cleans the silicon surfaces before the oxide layer forms. During photolithography, it rinses wafers after each exposure to remove residual photoresist. During chemical vapour deposition, it serves as a solvent and rinse. During chemical-mechanical planarisation, the polishing step that smooths wafer surfaces between circuit layers carries the polishing slurry and removes waste material. Across a full fabrication cycle of 300 to 600 process steps, water contacts the wafer dozens of times. Chemical mechanical polishing alone accounts for 30 to 40 percent of a fab's total wastewater volume..In a working 300mm fab, about 76 percent of all water withdrawn is directly tied to the manufacturing process. The remainder supports cooling towers and scrubbers that maintain cleanroom temperature and humidity within tolerances of ±0.1 degrees Celsius, a thermal load that generates continuous demand for cooling water on top of the process UPW system..How ultra-pure water is produced: the filtration chainProducing UPW from raw source water requires a sequenced multi-stage treatment train. No single technology bridges the gap from municipal supply to 18.2 megaohm-centimetres. Each stage removes a specific category of contamination and prepares the water for the next. Chart 2 illustrates the resistivity gain at each stage of the treatment chain..Pre-treatmentRaw water entering a UPW plant passes through coagulation and flocculation to remove suspended solids. Activated carbon filtration removes chlorine, chloramines, and dissolved organic precursors that would foul downstream membranes. Multimedia filters of sand, anthracite, and garnet capture remaining particulates. Softening via ion exchange reduces hardness to below 1 ppm. This stage matters especially for Gujarat, where Narmada Canal water carries seasonal sediment loads and agricultural runoff that varies between monsoon and dry seasons. Pre-treatment failure degrades downstream membrane performance and shortens resin life, raising operating costs throughout the system..Reverse osmosisPre-treated water enters a two-pass reverse osmosis system. RO membranes operating at 8 to 15 bar of applied pressure force water molecules through a semi-permeable barrier while rejecting dissolved salts, minerals, silica, and organic molecules above approximately 200 daltons in molecular weight. A well-designed first-pass RO system removes 95 to 99 percent of total dissolved solids, reducing TDS from 500 ppm to 5 to 25 ppm. The second pass achieves further reduction. RO technology held the largest revenue share of the global UPW treatment systems market; 40.6 percent in 2024, because it provides scalable, broad-spectrum contamination removal that no downstream polishing step can substitute..RO generates a reject stream that concentrates removed contaminants. To produce 1,000 gallons of UPW, approximately 1,400 to 1,600 gallons of raw municipal water are consumed. The shortfall is the reject stream, which carries concentrated contaminants and must be managed in accordance with India's Zero Liquid Discharge requirements..ElectrodeionisationRO permeate still contains ionic impurities at parts-per-billion levels. Electrodeionisation combines ion-exchange resin beds with ion-selective membranes and a direct-current electrical field. Ions are continuously drawn to electrode chambers and removed while resins are regenerated by the water itself, without acid or caustic regeneration chemicals. EDI eliminates the chemical waste streams associated with conventional deionisation. The EDI segment of the global UPW treatment systems market is projected to grow at 7.9 percent compound annual growth through 2033, the fastest of any technology segment, because it replaces chemical-intensive systems that generate secondary waste treatment requirements..Polishing and the closed loopPost-EDI water enters a polishing loop. UV oxidation at 185nm wavelength breaks down trace organic molecules, photoresist fragments, and biological metabolites into carbon dioxide and water, reducing total organic carbon to below one part per billion. Ultrafiltration membranes with 0.01- to 0.02-micron pore sizes remove sub-micron particles and any residual bacteria. Final mixed-bed ion-exchange polishers achieve a resistivity of 18.2 megaohm-centimetres. Membrane degasification removes dissolved oxygen and carbon dioxide. The entire polishing loop is constructed from high-purity materials: PVDF, PFA, or electropolished stainless steel that do not leach contaminants..The UPW loop in a working fab runs continuously. UPW in contact with atmospheric carbon dioxide degrades in resistivity within hours. Point-of-use monitoring inline sensors for resistivity, total organic carbon, particle counts, and dissolved oxygen operates continuously and is integrated with the facility management system to divert flow before off-specification water reaches any process tool.UPW Quality Targets for Semiconductor Manufacturing (28nm Node): Resistivity: 18.2 MΩ·cm at 25°CTotal Organic Carbon: below 1 ppb Particles: below 1 per mL above 0.05 µmBacteria: below 0.1 CFU/mLDissolved oxygen: below 1 ppbDissolved silica: parts per trillion control Source: AXEON Water (2026), IDE Tech (2024).Chart 4 maps daily water demand at Dholera over the ramp from initial pilot production to the planned peak capacity of 50,000 wafer starts per month. The benchmark of 1,500 gallons of UPW per 300mm wafer and 2,200 gallons of total water is drawn from IDE Tech and AXEON Water's semiconductor water use analyses. At 50,000 wafers per month, raw municipal water input reaches approximately 3.7 to 4 million gallons per day at full utilisation..This is not a peak demand figure; it is the steady-state operational draw. A fab that runs at 90 percent utilisation draws water at 90 percent of full capacity every day. The Gujarat industrial water tariff and Dholera's dedicated water pipelines, referenced in the ISM facility infrastructure documentation, address the connection question. They do not address the source-capacity question: whether the Narmada Canal system's available allocation for Dholera's industrial zone, net of agricultural and municipal commitments, can sustain this demand over a 30-year facility lifecycle that will include years of drought and seasonal variation..The wastewater challenge: ZLD in a water-scarce stateUPW does not leave the fab clean. Each process step contaminates the water with the materials from that step. Photolithography rinse water carries photoresist polymers and solvent residues. Etching baths leave fluoride, hydrofluoric acid derivatives, and metal ions copper, arsenic, cobalt, chromium from the wafer surface being etched. CMP rinse water carries polishing slurry particles and the metals removed from the wafer surface. A large fab generates 15 to 18 distinct wastewater streams with varying chemistries, concentrations, and treatment requirements..India's environmental regulatory framework under the Water (Prevention and Control of Pollution) Act, 1974, and the Environment (Protection) Act, 1986, mandates Zero Liquid Discharge for industrial facilities. ZLD means no liquid wastewater leaves the site boundary. Every litre is treated and recycled internally, or reduced to dry solid waste for managed disposal. The Central Pollution Control Board and State Pollution Control Boards enforce ZLD compliance, and environmental clearances now require water balance charts and reuse plans as part of the Detailed Project Report..For semiconductor fabs, ZLD is both a regulatory requirement and an operational advantage. A fab that recycles 70 to 75 percent of its process water, the current industry average requires substantially less raw water input than a once-through system. The technical challenge is achieving high recycling rates from semiconductor wastewater. Low-level rinse waters can be recovered through RO and polishing relatively straightforwardly. High-concentration streams from etch baths, CMP slurry waste, and chemical cleaning require intensive treatment: pH neutralisation, metals precipitation, advanced oxidation, membrane concentration, and sometimes evaporative crystallisation to produce a dry solid residue..The CPCB's current effluent framework does not have semiconductor-specific discharge standards. It applies general industrial norms, a fluoride limit of 2 mg/L for inland discharge, with maximum concentrations for arsenic, mercury, lead, chromium, copper, and cobalt, to a waste stream category whose composition and treatment requirements are technically distinct from conventional industrial effluent. Sector-specific standards, analogous to those for tanneries, distilleries, and textiles, would provide the clarity on compliance that fab operators need at the design stage.TSMC achieved a process water recycling rate of 90.3 percent across its Taiwan fabs in 2023. UMC's Fab 12A in Taiwan reached 90.8 percent. SK Hynix increased its reused water volume by 51 percent between 2020 and 2023, motivated by water stress classifications at three of its fabs. TSMC's Southern Taiwan Science Park reclaimed water plant, the world's first industrial reclaimed water plant dedicated to semiconductor processes, supplied over 67,000 metric tonnes of reclaimed water per day to TSMC's Tainan fabs by the end of 2024, contributing a 17 percent replacement of city water at those sites. In 2024, TSMC's total wastewater recycling exceeded 140 million cubic metres..These rates were achieved under sustained operational pressure and significant capital investment over a decade. TSMC began investing in water recycling in 2015, specifically to reduce dependence on municipal supply after Taiwan's 2021 drought forced emergency water trucking to maintain fab operations. The lesson for India is not that 90 percent recycling is immediately achievable at first silicon, it is that the design choices made during construction determine how efficiently the recycling trajectory improves over the first five years of operation. .India's new fabs should target an 85 percent process water recycling rate within three years of commercial operation. Achieving this requires designing ZLD treatment capacity for peak load from the start rather than retrofitting it after production pressure mounts, implementing wastewater stream segregation by contamination tier from day one, and adopting point-of-use chemical blending and counter-flow rinsing that reduce waste load per wafer before treatment is needed..The global UPW treatment systems market was valued at USD 10.4 billion in 2024. The semiconductor segment held the largest application share at 41.5 percent of the total, driven by wafer fabrication's stringent purity requirements. Asia-Pacific dominated the market with a 39.8 percent revenue share in 2024. The market is projected to reach USD 16 billion by 2033, growing at a compound annual rate of 4.7 percent. The EDI segment, the most relevant technology for India's needs given its chemical-free operation, is the fastest-growing segment within the market..India's semiconductor buildout, combined with its pharmaceutical and advanced battery manufacturing pipelines, places it directly in the growth trajectory of this market. Most fab-grade UPW system integrators with semiconductor-specific experience are based in the United States, Europe, South Korea, and Taiwan. India has capable water treatment firms: Praj HiPurity Systems, Wipro Water, and Aquamech, with engineering competence in RO and EDI for pharmaceutical and electronics applications. The gap is in semiconductor-specific system integration: designing UPW loops rated for 18.2 megaohm-centimetres, specifying point-of-use monitoring at parts-per-billion TOC resolution, and building the recirculation infrastructure that keeps UPW quality stable under the variable loads of a multi-tool cleanroom..CSIR-CSMCRI, the Central Salt and Marine Chemicals Research Institute in Bhavnagar, published a scalable RO-EDI technology in May 2026, independently validated in India, and configured for up to 100,000 litres per day in modular form. This addresses a gap that had previously forced domestic industrial projects to license UPW process routes from foreign suppliers. ISM 2.0's stated focus on equipment, materials, and indigenous IP, the four pillars of the new mission phase, provides a policy frame for extending this to semiconductor-grade UPW system integration. Credit guarantees, R&D grants, or pilot facility funding aligned to CSIR-CSMCRI and similar domestic technology developments would translate roadmap language into investable outcomes for the domestic water technology sector..The policy gap and what needs to close itIndia's semiconductor and water policies currently operate on parallel tracks. The India Semiconductor Mission, under MeitY, manages the fab investment pipeline. The Ministry of Jal Shakti manages national water policy and industrial allocation frameworks. The Central Pollution Control Board sets discharge standards. State Pollution Control Boards enforce them. None of these bodies has a formal coordination mechanism specific to semiconductor water infrastructure..This creates concrete problems. Water tariff commitments at the state level do not automatically come with volume guarantees, quality specifications for source water, or monsoon-season variability assessments that a fab operator needs to size UPW pre-treatment systems. Environmental clearance processes that require water balance charts do not currently benchmark against semiconductor-specific UPW quality requirements or ZLD recycling targets. Sector-specific CPCB standards for semiconductor wastewater do not exist, creating compliance uncertainty during fab design..Three policy actions would close the most consequential gaps. First, MeitY and the Ministry of Jal Shakti should jointly commission water assessments for each approved semiconductor facility, covering source water quality characterisation, peak-demand modelling under full utilisation, and the identification of supply-augmentation requirements where existing canal or treatment capacity is insufficient. Second, CPCB should develop semiconductor-specific effluent standards that classify wastewater streams by contamination tier and specify treatment requirements and recycling targets for each tier. Third, ISM 2.0 should include UPW system integration capability as an explicit target within its equipment and materials pillar, with support mechanisms aligned to domestic technology developments at CSIR-CSMCRI and India's water treatment industry..The NITI Aayog roadmap released on May 29, 2026, lists ultra-pure water supply as an infrastructure requirement for integrated semiconductor manufacturing clusters. Moving from that acknowledgement in a planning document to allocated responsibility, timelines, and budget in implementation plans is the work that needs to happen before first silicon at Dholera in late 2026..Water quality as a yield variable: the economic caseThe strongest argument for treating water infrastructure as a first-priority investment is yield. A fab producing 50,000 wafers per month at 80 percent yield generates 40,000 wafers of sellable output. At 70 percent yield, it generates 35,000 wafers. At market prices for automotive and industrial chips in the 28nm to 110nm range, the segment targeted at Dholera, the revenue difference between those two yield rates runs into hundreds of millions of dollars annually at scale..Yield losses in a new fab come from many sources: process recipe optimisation, equipment calibration, operator training, and supply chain quality. Water quality is one of the controllable variables. A fab that enters pilot production with UPW systems designed to source water specification, ZLD treatment capacity adequate for peak load, and process tools configured for water-efficient operation will start yield ramp from a more stable baseline than one operating with water quality variability or treatment shortfalls. At the Dholera timeline- first silicon in late 2026, commercial production in 2028- the water infrastructure design decisions are being made now. They are construction-phase decisions. Changing them after production starts is expensive and disruptive..Advanced semiconductor fabs in Arizona and Taiwan have already experienced the consequences of underweighting water risk in facility planning. Arizona's chip investments face long-term groundwater depletion concerns that directly affect operational security assessments. Taiwan's manufacturers competed with 23 million residents for water during the 2021 drought and operated emergency trucking to maintain supply. TSMC has invested in water recycling since 2015 specifically to reduce that exposure, and still missed its 2023 water consumption reduction target because production growth outpaced efficiency gains. India enters its semiconductor buildout before these constraints have become acute, but that advantage is only available if water planning is done rigorously during construction..ConclusionIndia's chip programme is real and operational. Micron's ATMP in Sanand is in commercial production. Kaynes Semicon launched in March 2026. Tata-PSMC in Dholera is 50 percent built and signed an ASML equipment partnership in May 2026. Budget 2026-27 allocated Rs 8,000 crore to the mission. The ISM website now records active and upcoming production milestones..What the public conversation about this programme has not yet engaged with at sufficient depth is water. Ultra-pure water at 18.2 megaohm-centimetres is not a commodity. It requires a multi-stage treatment train from source to point of use, continuous quality monitoring at parts-per-billion resolution, water-efficient process design, and a Zero Liquid Discharge system sophisticated enough to handle 15 to 18 distinct contaminated wastewater streams. Each of these elements requires capital, engineering capability, and regulatory clarity that India is still building..The domestic UPW technology base is developing: Praj HiPurity, Wipro Water, CSIR-CSMCRI's May 2026 publication. The regulatory framework needs semiconductor-specific effluent standards from CPCB. ISM 2.0 needs an explicit UPW system integration target within its equipment and materials pillar. And MeitY and Jal Shakti need a shared coordination mechanism for water supply at approved fab sites before water demand becomes operational rather than notional..India is building the first stage of its semiconductor programme on commitments about power, land, capital, and talent. Water is the next commitment that needs to be made — in infrastructure, policy, and engineering standards — before the fabs produce chips, and the constraints that should have been addressed during construction become yield problems on the production floor..About the AuthorSagari Gupta is an independent Public Policy Researcher. With over eight years of experience spanning NCAER, the Ministry of Consumer Affairs, and the Institute for Human Development, her work covers public policy, AI ethical governance, and philosophy-informed research. She holds an MPhil and MA in Philosophy from Delhi University and an MA in Economics from IGNOU. Her policy journalism appears in Down to Earth, Moneycontrol, Deccan Herald, Policy Circle, Mint, and other national publications.